Erasable programmable read only memories, known as EPROMs, and electrically erasable programmable read only memories, known as EEPROMs, are well known "floating gate" devices of the art. Typically, these double layer polysilicon non-volatile memory devices are programmed and accessed using a separate device which is electrically coupled to the memory device. In the past, such programming and accessing has been accomplished using a transistor formed during the formation of the memory device. That is, the formation of the transistor was incorporated into the manufacturing process flow of the memory device. Specifically, as the second layer of polysilicon was deposited to form the memory cell, the polysilicon was also deposited onto a separate region of the substrate. A transistor was then formed in that separate region having the second layer of polysilicon as one of the gates of the device. Incorporating the formation of the transistor into the manufacturing process flow was considered to be advantageous in that it simplified the manufacturing processes required in the formation of the devices.
Accessing the floating gate device using a high performance submicron CMOS transistor would be especially beneficial due to the high speed at which the submicron CMOS device operates. However, several incompatibilities exist which inhibit integrating the formation of submicron CMOS devices, such as high performance N-channel and P-channel transistors, with the manufacturing processes used to form double layer polysilicon non-volatile memory devices such as EPROMs and EEPROMs.
Floating gate devices, such as EPROMs and EE-PROMs, require significant oxidation after the deposition of each of the polysilicon layers forming these devices. Multiple poly re-oxidations are necessary to achieve adequate charge retention characteristics. Unfortunately, submicron CMOS devices experience significant transconductance and reliability degradation when exposed to excessive poly re-oxidation. As a result, performance of submicron CMOS devices exposed to dual-poly formation processes is prohibitively reduced. Specifically, as submicron polysilicon gates are exposed to repeated oxidation, the edges of the gates tend to lift from the substrate due to oxidation of the gate edges. This decouples the gate from the channel region. As a result, gain degradation and hot electron reliability problems occur. Additionally, the re-oxidation thermal cycle causes dopant diffusion of the channel's voltage adjust implant.
Furthermore, the operation of dual-poly non-volatile memory devices is often incompatible with the use of high performance submicron CMOS devices. EPROMs and EEPROMs frequently require relatively high programming voltages of 12-18 volts. Such voltages are incompatible with thin gate oxides and lower diode breakdowns found in submicron CMOS devices. Submicron CMOS devices typically have thin gate oxide thicknesses of less than 200 angstroms. A gate oxide of less than 200 angstroms, however, has an intrinsic breakdown of approximately 15 volts. Therefore, the programming voltages utilized in dual-poly non-volatile memory elements essentially destroy high performance submicron CMOS devices.
Therefore it is an object of the present invention to successfully integrate the formation and use of high performance submicron CMOS devices with the manufacture and operation of dual-poly non-volatile memory devices.